Memory system and related block management method

ABSTRACT

A memory system manages memory blocks of a nonvolatile memory device by determining at least one memory block property of a selected memory block among the multiple memory blocks in the nonvolatile memory device, storing memory block property information indicating the at least one memory block property, arranging a free memory block list based on the stored memory block property information, and designating a free memory block from the arranged free memory block list as an active memory block, wherein the designation of the free memory block as an active memory block is based on an ordering of the free memory block list.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2013-0010019 filed on Jan. 29, 2013, the subjectmatter of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The inventive concept relates generally to electronic memorytechnologies. More particularly, certain embodiments of the inventiveconcept relate to memory systems and block management methods for thememory systems.

Memory devices are generally subject to deterioration according tousage. In some devices, deterioration may occur on a memory cell bymemory cell basis. For example, individual memory cells in a flashmemory may fail after they are programmed, erased, or read apredetermined number of times.

To prevent some memory cells from failing well before others, memorydevices often implement so-called wear-leveling schemes to ensure thatmemory cells are used—and therefore wear out—at a similar rate. Suchwear-leveling schemes typically keep track of the number of accessoperations (e.g., erase and/or program operations) performed on eachmemory cell or group of memory cells (e.g., a memory block), and theyselect memory cells to be programmed or erased based on the number. Forinstance, a memory block that has been programmed or erased fewer timesmay be selected so that some memory blocks are not erased substantiallymore than others.

A drawback of conventional wear-leveling schemes is that they generallyignore small variations between individual memory cells. For instance,by equalizing the number of access operations performed on differentmemory cells, these schemes assume that the memory cells are destined toendure approximately the same number of access operations, even thoughthey may in fact differ substantially in their actual endurance.Consequently, these schemes may lead to relatively high bit error rates(BERs) and early failure for some memory blocks and relatively low BERsand later failure for others.

SUMMARY OF THE INVENTION

In one embodiment of the inventive concept, a method is provided formanaging memory blocks in a memory system comprising a nonvolatilememory device. The method comprises determining at least one memoryblock property of a selected memory block among the multiple memoryblocks in the nonvolatile memory device, storing memory block propertyinformation indicating the at least one memory block property, arranginga free memory block list based on the stored memory block propertyinformation, and designating a free memory block from the arranged freememory block list as an active memory block, wherein the designation ofthe free memory block as an active memory block is based on an orderingof the free memory block list.

In another embodiment of the inventive concept, a memory systemcomprises a nonvolatile memory device comprising multiple memory blocksand a meta area, and a memory controller configured to control thenonvolatile memory device. The meta area stores erase count information,a ready-to-use list of memory blocks, a long term list of memory blocks,and memory block retry information for memory blocks in the ready-to-uselist and the long term list. The memory controller performs awear-leveling operation on the memory blocks using the erase count andthe memory block retry information. The ready-to-use list is a list ofmemory blocks each having a relatively low threshold voltage offset, thelong term list is a list of memory blocks each having a relatively highthreshold voltage offset, and the memory block retry information isobtained from read retry operations performed on the memory blocks inthe ready-to-use list and the long term list.

These and other embodiments of the inventive concept can potentiallyimprove the reliability of a nonvolatile memory device by performingwear leveling according to both usage information of memory blocks, aswell as operational characteristics of the memory blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate selected embodiments of the inventive concept.In the drawings, like reference numbers indicate like features.

FIG. 1 is a memory block diagram illustrating a memory system accordingto an embodiment of the inventive concept.

FIG. 2 is a diagram illustrating life-cycle of memory blocks illustratedin FIG. 1.

FIG. 3 is a diagram illustrating a read retry operation of a memoryblock having memory cells with relatively low threshold voltage offsets.

FIG. 4 is a diagram illustrating a read retry operation of a memoryblock having memory cells with relatively high threshold voltageoffsets.

FIG. 5 is a diagram illustrating a method of managing free memory blocksaccording to an embodiment of the inventive concept.

FIG. 6 is a diagram illustrating a method of sorting a ready-to-use listof memory blocks according to an embodiment of the inventive concept.

FIG. 7 is a diagram illustrating a method of sorting a long term list ofmemory blocks according to an embodiment of the inventive concept.

FIG. 8 is a flowchart illustrating a method of performing wear-levelingin a memory system according to an embodiment of the inventive concept.

FIG. 9 is a flowchart illustrating a method of performing blockmanagement in a memory system according to an embodiment of theinventive concept.

FIG. 10 is a memory block diagram illustrating a solid state driveaccording to an embodiment of the inventive concept.

FIG. 11 is a memory block diagram illustrating an eMMC according to anembodiment of the inventive concept.

DETAILED DESCRIPTION

Embodiments of the inventive concept are described below with referenceto the accompanying drawings. These embodiments are presented asteaching examples and should not be construed to limit the scope of theinventive concept.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art. Terms such as those defined in commonlyused dictionaries should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present specification and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

FIG. 1 is a memory block diagram illustrating a memory system 10according to an embodiment of the inventive concept.

Referring to FIG. 1, memory system 10 comprises at least one nonvolatilememory device 100 and a memory controller 200 controlling nonvolatilememory device 100.

For explanation purposes, it will be assumed that nonvolatile memorydevice 100 is a NAND flash memory device, although the inventive conceptis not limited to a NAND flash memory device. For example, conceptsdescribed with reference to nonvolatile memory device 100 could also beapplied to a NOR flash memory device, a Resistive Random Access Memory(RRAM) device, a Phase-Change Memory (PRAM) device, a MagnetroresistiveRandom Access Memory (MRAM) device, a Ferroelectric Random Access Memory(FRAM) device, a Spin Transfer Torque Random Access Memory (STT-RAM),and the like. Further, the nonvolatile memory device can be implementedto have a three-dimensional array structure. The inventive concept maybe applied to a Charge Trap Flash (CTF) memory device including a chargestorage layer formed of an insulation film as well as a flash memorydevice including a charge storage layer formed of a conductive floatinggate.

Nonvolatile memory device 100 comprises multiple memory blocks BLK0 toBLKz, each comprising multiple cell strings. Each cell string typicallycomprises at least one string selection transistor, multiple memorycells, and at least one ground selection transistor which are connectedin series. Each of the memory cells may store at least one bit of data,and may be driven by a voltage transferred through a corresponding oneof word lines.

A meta area 110 stores management information used to manage nonvolatilememory device 100. Meta area 110 stores a ready-to-use list 111, a longterm list 112, and memory block retry information 113. Ready-to-use list111 is a list of memory blocks having a memory cells with relatively lowthreshold voltage offsets, and long term list 112 is a list of memoryblocks having memory cells with relatively high threshold voltageoffsets.

The relatively low and high threshold voltage offsets are determinedthrough a read retry operation in which a sequence of different readvoltages are applied to selected memory cells until the memory cells aresuccessfully read. The read retry operation typically applies an initialdefault read voltage to the selected memory cells and then eitherincreases or decreases the default read voltage until a desired outcomeis achieved. For instance, in an example illustrated in FIG. 3, a readvoltage is decreased until it falls below an upper one of two adjacentthreshold voltage distributions of the selected memory cells. Similarly,in an example illustrated in FIG. 4, a read voltage is increased untilit rises above a lower one of two adjacent threshold voltagedistributions of the selected memory cells.

Where the read voltage required to successfully read the selected memorycells is greater than the default read voltage, the selected memorycells (or alternatively, memory block) are deemed to have a relativelyhigh threshold voltage offset. More particularly, their thresholdvoltages are deemed to have a positive offset relative to the defaultread voltage. On the other hand, where the read voltage required tosuccessfully read the selected memory cells is less than the defaultread voltage, the selected memory cells (or alternatively, memory block)are deemed to have a relatively low threshold voltage offset. Moreparticularly, their threshold voltages are deemed to have a negativeoffset relative to the default read voltage. The use of the terms“relatively low” and “relatively high” in this context merely indicatesthat the relatively low threshold voltage offset is below the relativelyhigh threshold voltage offset.

Memory block retry information 113 comprises an offset voltage andaddress information for a memory block. The offset voltage indicatesactual offset of the read voltage required to successfully read theselected memory cells.

Ready-to-use list 111 and long term list 112 may be determined based onmemory block retry information 113. For example, where an offset voltageis a negative value (e.g., a memory cell has a relatively low thresholdvoltage offset), a memory block corresponding to address information maybe included in ready-to-use list 111. On the other hand, where an offsetvoltage is a positive value (e.g., a memory cell has a relatively highthreshold voltage offset), a memory block corresponding to addressinformation may be included in long term list 112.

Memory controller 200 controls nonvolatile memory device 100. Memorycontroller 200 comprises a memory block management unit 220 to managethe memory blocks BLK0 to BLKz.

Memory block management unit 220 manages wear-leveling of the memoryblocks BLK0 to BLKz based on memory block usage information and propertyinformation of memory cells (or, memory blocks). In other words, incontrast to certain conventional approaches that merely use memory blockusage information, memory block management unit 220 manageswear-leveling based on the usage and the properties of memory cellsand/or memory blocks. The memory block usage information typicallycomprises an erase count, a program count, and/or a read count. Althoughnot shown in FIG. 1, the memory block usage information may be stored atmeta area 110. Also, the memory cell property information may be memoryblock retry information 113 associated with retention or endurance.

After a read retry operation is performed on a memory block, memoryblock management unit 220 stores memory block retry information 113associated with the read retry operation in meta area 110. Memory blockmanagement unit 220 sorts ready-to-use list 111 and long term list 112based on memory block retry information 113. Memory block managementunit 220 may assign a memory block, having the best relatively lowthreshold voltage offset, from among free memory blocks to an activememory block for a data write operation.

In contrast to conventional systems, memory system 10 may performwear-leveling in consideration of both an erase count and memory cellproperties, such as a threshold voltage offset. This can be accomplishedthrough the use of ready-to-use list 111 and long term list 112, as willbe apparent from the description that follows.

FIG. 2 is a diagram illustrating life-cycle of blocks BLK0 to BLKz ofFIG. 1.

Referring to FIG. 2, first, an unused block 121 is in an erase state.Unused block 121 can be designated as an active memory block 122 inwhich data is to be written. If data is successfully written in activememory block 122 assigned, active memory block 122 may be designated asa valid memory block 123. Where a write operation on active memory block122 fails, the active memory block may be designated as a bad memoryblock 124. Otherwise, if data of valid memory block 123 is determined tobe invalid in a merge operation, valid memory block 123 may bedesignated as an invalid memory block 125.

If an erase operation is successfully performed, invalid memory block125 may be designated as a free memory block 126. Free memory block 126may be designated as a ready-to-use block 127 or a long term block 128according to a memory cell property (e.g., a threshold voltage offsetdetermined by a read retry operation). Ready-to-use block 127 is a freememory block comprising memory cells each having a relatively lowthreshold voltage offset, and the long term block 128 may be a freememory block comprising memory cells each having an relatively highthreshold voltage offset. Ready-to-use block 127 may be newly designatedas an active memory block 122. For example, ready-to-use block 127having a lowest threshold voltage offset may be designated as an activememory block 122. Long term block 128 may be designated as aready-to-use block 127 after a predetermined lapse of time.

Meanwhile, if an erase operation fails, invalid memory block 125 may bedesignated as a bad memory block 124. In some situations, although notshown in FIG. 2, the bad memory block 124 can be designated as a freememory block 126 if an erase operation is successfully performed under apredetermined condition.

FIG. 3 is a diagram illustrating a read retry operation for a memoryblock having a relatively low threshold voltage offset, and FIG. 4 is adiagram illustrating a read retry operation for a memory block having arelatively high threshold voltage offset. In each of FIGS. 3 and 4,solid curves represent ideal threshold voltage distributions of selectedmemory cells, and dotted curves represent actual threshold voltagedistributions that may exist among selected memory cells. As indicatedby a tallest vertical line in each of FIGS. 3 and 4, a default readvoltage Vdflt falls between the ideal threshold voltage distributions,and could be used to read the selected memory cells if their thresholdvoltage distributions did not deviate from the ideal. Meanwhile, shortervertical lines indicate read voltages used in successive iterations ofthe read retry operation. A threshold voltage offset Vost represents adifference between the default read voltage Vdflt and a read voltagethat results in successful reading of the selected memory cells.

Referring to FIG. 3, the read retry operation proceeds by decreasing theread voltage from default read voltage Vdflt in successive iterations.The read retry operation is generally successful once the read voltagefalls below an upper one of two threshold voltage distributions. Oncethis occurs, a memory block property is determined to be “relatively lowthreshold voltage offset”, and corresponding block retry information isstored as memory block retry information 113. Memory block retryinformation 113 may be, for instance, a bit or a value indicative of therelatively low threshold voltage offset, or it may be a read retrynumber corresponding to the offset voltage Vost. As used in thisdescription, the term “memory block property” denotes an operationalcharacteristic of memory cells belonging to a memory block, as opposedto mere historical information, such as an erase count, for example.

Referring to FIG. 4, the read retry operation proceeds by increasing theread voltage from default read voltage Vdflt in successive iterations.The read retry operation is generally successful once the read voltagerises above a lower one of two threshold voltage distributions. Oncethis occurs, a memory block property is determined to be “relativelyhigh threshold voltage offset”, and corresponding block retryinformation is stored as memory block retry information 113. Memoryblock retry information 113 may be, for instance, a bit or a valueindicative of the relatively high threshold voltage offset, or it may bea read retry number corresponding to the offset voltage Vost.

FIG. 5 is a diagram illustrating a method of managing free memory blocksaccording to an embodiment of the inventive concept.

Referring to FIG. 5, a free memory block list comprises a ready-to-uselist and a long term list. The ready-to-use list indicates memory blockshaving a relatively low threshold voltage offset. The long term listcomprises memory blocks having an relatively high threshold voltageoffset. The memory blocks listed in the long term list may besubsequently transferred to the ready-to-use list after a predeterminedlapse of time, e.g., several weeks or months.

FIG. 6 is a diagram illustrating a method of sorting a ready-to-use listof memory blocks according to an embodiment of the inventive concept.

Referring to FIG. 6, the ready-to-use list is sorted sequentiallyaccording to a determined threshold voltage offset, starting with amemory block address “0x25” having a largest threshold voltage offset.The first memory block in the list will be the first memory block to bere-designated as an active memory block according to the life-cycleillustrated in FIG. 2.

FIG. 7 is a diagram illustrating a method of sorting a long term list ofmemory blocks according to an embodiment of the inventive concept.

Referring to FIG. 7, the long term list is sorted sequentially accordingto a determined threshold voltage offset, starting with a memory blockaddress “0x25” having a smallest threshold voltage offset. The firstmemory block in the list will be the first memory block to bere-assigned to the ready-to-use list according to the life-cycleillustrated in FIG. 2.

FIG. 8 is a flowchart illustrating a method of performing wear-levelingin a memory system according to an embodiment of the inventive concept.

Referring to FIGS. 1 to 8, the method determines whether an invalidmemory block erase count (BLK EC) is less than an average erase count(Avg. EC) (S110). If the memory block erase count is less than theaverage erase count, garbage collection may be performed on the memoryblock. The garbage collection operation is intended to reclaim invalidmemory blocks as free memory blocks. The garbage collection operationmay comprise, for instance, erasing an invalid memory block andperforming a read retry operation on the erased memory block. During theread retry operation, the method may determine and set memory blockretry information 113, as illustrated for instance, in FIGS. 3 and 4(S120).

Thereafter, the method determines whether the memory block retryinformation 113 indicates that the memory block has a relatively low orrelatively high threshold voltage offset (S130). If so, the memory blockis assigned to the ready to use list (S140), and if not, the memoryblock is assigned to the long term list (S145).

Following operations S140 and S145, data is programmed in a first memoryblock in the ready to use list (S150).

Although the above description assumes that a memory block property isdetermined by a read retry operation, the inventive concept is notlimited to this type of determination. For example, in alternativeembodiments a memory block property may be determined according to othermethods.

FIG. 9 is a flowchart illustrating a method of managing memory blocks ina memory system according to an embodiment of the inventive concept.

Referring to FIG. 9, the method determines whether a memory block has arelatively low threshold voltage offset or a relatively high thresholdvoltage offset (S210). Under these circumstances, the threshold voltageoffset may be expressed, for example, as a numerical value. Next, memoryblock property information, including a the threshold voltage offset, isstored (S220). Then, a free memory block list is arranged (e.g., sorted)based on the stored memory block property information (S230). Here, thefree memory block list may be arranged so that a memory block having alower threshold voltage offset (i.e., more negative or less positive) isto be preferentially designated as an active memory block. Then, anactive memory block is selected from the free memory blocks arranged toprogram data (S240).

FIG. 10 is a memory block diagram illustrating a solid state driveaccording to an embodiment of the inventive concept.

Referring to FIG. 10, a solid state drive (SSD) 1000 comprises multipleflash memory devices 1100 and an SSD controller 1200. Flash memorydevices 1100 may be configured to receive an external high voltage VPPx.A wear-leveling method described with reference to FIGS. 1 to 9 may beapplied to each flash memory device 1100. SSD controller 1200 may beconnected to flash memory devices 1100 via multiple channels CH1 to CHi.SSD controller 1200 comprises at least one processor 1210, a buffermemory 1220, a host interface 1250, and a flash interface 1260.

FIG. 11 is a memory block diagram illustrating an embedded MMC (eMMC)according to an embodiment of the inventive concept.

Referring to FIG. 11, an eMMC 2000 comprises at least one NAND flashmemory device 2100 and controller 2200 integrated in a chip. NAND flashmemory device 2100 may be a single data rate (SDR) NAND flash memorydevice or a double data rate (DDR) NAND flash memory device. In exampleembodiments, the NAND flash memory device 2100 may comprise NAND flashmemory chips. Herein, the NAND flash memory device 2100 may beimplemented by stacking the NAND flash memory chips at one package(e.g., FBGA, Fine-pitch Ball Grid Array, etc.). A wear-leveling or blockmanagement method described with reference to FIGS. 1 to 9 may beapplied to each NAND flash memory device.

Controller 2200 may be connected with the flash memory device 2100 viamultiple channels. Controller 2200 comprises at least one controllercore 2210, a host interface 2110, and a NAND interface 2260. Controllercore 2210 controls overall operations of eMMC 2000. Host interface 2110may be configured to interface between controller 2210 and a host. NANDinterface 2260 is configured to provide an interface between NAND flashmemory device 2100 and controller 2200. Host interface 2110 may be aparallel interface (e.g., an MMC interface). In other exampleembodiments, host interface 2110 of eMMC 2000 may be a serial interface(e.g., UHS-II, UFS, etc.).

EMMC 2000 typically receives power supply voltages Vcc and Vccq from thehost. Herein, the power supply voltage Vcc (about 3.3V) may be suppliedto the NAND flash memory device 2100 and the NAND interface 2260, andthe power supply voltage Vccq (about 1.8V/3.3V) may be supplied tocontroller 2200.

EMMC 2000 is applicable to small-sized and low-power mobile products(e.g., Galaxy S series, Galaxy note series, iPhone, iPad, Nexus, etc.).

The foregoing is illustrative of embodiments and is not to be construedas limiting thereof. Although a few embodiments have been described,those skilled in the art will readily appreciate that many modificationsare possible in the embodiments without materially departing from thescope of the inventive concept. Accordingly, all such modifications areintended to be included within the scope of the inventive concept asdefined in the claims.

What is claimed is:
 1. A method of managing memory blocks in a memorysystem comprising a nonvolatile memory device, comprising: determiningat least one memory block property of a selected memory block among themultiple memory blocks in the nonvolatile memory device; storing memoryblock property information indicating the at least one memory blockproperty; arranging a free memory block list based on the stored memoryblock property information; and designating a free memory block from thearranged free memory block list as an active memory block, wherein thedesignation of the free memory block as an active memory block is basedon an ordering of the free memory block list.
 2. The method of claim 1,wherein the at least one memory block property is determined byperforming a read retry operation on the selected memory block.
 3. Themethod of claim 2, wherein the memory block property indicates that theselected memory cell has a relatively low threshold voltage offset. 4.The method of claim 2, wherein the memory block property indicates thatthe selected memory cell has a relatively high threshold voltage offset.5. The method of claim 2, wherein the memory block property informationcomprises memory block retry information of the read retry operation. 6.The method of claim 1, wherein the free memory block list comprises aready-to-use list and a long term list, wherein the ready-to-use list isa list of memory blocks each having a relatively low threshold voltageoffset, and the long term list is a list of memory blocks each having arelatively high threshold voltage offset.
 7. The method of claim 6,wherein the arranging the free memory block list based on the memoryblock property information comprises: assigning the selected memoryblock to the ready-to-use list where a read retry operation of theselected memory block indicates that the selected memory block has arelatively low threshold voltage offset.
 8. The method of claim 7,wherein the arranging the free memory block list based on the memoryblock property information further comprises: arranging the ready-to-uselist according to a threshold voltage offset of each memory block in theready-to-use list.
 9. The memory block management method of claim 6,wherein the arranging the free memory block list based on the memoryblock property information comprises: where a read retry operation ofthe selected memory block indicates that the selected memory block has arelatively high threshold voltage offset.
 10. The memory blockmanagement method of claim 9, wherein the arranging the free memoryblock list based on the memory block property information furthercomprises: arranging the long term list according to a threshold voltageoffset of each memory block in the long term list.
 11. The memory blockmanagement method of claim 6, wherein the arranging the free memoryblock list based on the memory block property information comprises:reassigning a memory block in the long term list to the ready-to-uselist based on an elapsing of a predetermined time.
 12. The memory blockmanagement method of claim 6, further comprising identifying a memoryblock having a lowest threshold voltage offset among memory blocks inthe free memory block list, and designating the identified memory blockas an active block.
 13. The memory block management method of claim 1,further comprising: determining whether an erase count of the selectedmemory block is less than an average block erase count for memory blocksin the nonvolatile memory device; and performing a wear-levelingoperation using the memory block property information where the erasecount of the selected memory block is less than the average block erasecount.
 14. A memory system, comprising: a nonvolatile memory devicecomprising multiple memory blocks and a meta area; and a memorycontroller configured to control the nonvolatile memory device, whereinthe meta area stores erase count information, a ready-to-use list ofmemory blocks, a long term list of memory blocks, and memory block retryinformation for memory blocks in the ready-to-use list and the long termlist; wherein the memory controller performs a wear-leveling operationon the memory blocks using the erase count and the memory block retryinformation; and wherein the ready-to-use list is a list of memoryblocks each having a relatively low threshold voltage offset, the longterm list is a list of memory blocks each having a relatively highthreshold voltage offset, and the memory block retry information isobtained from read retry operations performed on the memory blocks inthe ready-to-use list and the long term list.
 16. The memory system ofclaim 16, wherein the memory block retry information indicates whethereach of the memory blocks in the ready-to-use list and the long termlist has a relatively low threshold voltage offset or a relatively highthreshold voltage offset.
 17. The memory system of claim 14, whereinfree memory blocks are generated by erasing invalid memory blocks amongthe multiple memory blocks, and the free memory blocks are designated asready-to-use blocks or long term blocks based on the memory block retryinformation.
 18. The memory system of claim 14, wherein the ready-to-uselist is a list of memory blocks each having a relatively low thresholdvoltage offset, and the long term list is a list of memory blocks eachhaving a relatively high threshold voltage offset.
 19. The memory systemof claim 18, wherein a selected memory block to the ready-to-use listwhere a read retry operation of the selected memory block indicates thatthe selected memory block has a relatively low threshold voltage offset,and assigning the selected memory block to the long term list where theread retry operation indicates that the selected memory block has arelatively high threshold voltage offset.
 20. The memory system of claim18, wherein the ready-to-use list and the long term list are eacharranged according to a threshold voltage offset of each memory block inthose lists.